The present invention relates to integrated circuit packaging of computer systems and more particularly to structures that allow some flexibility in computer architectures so that program and command word-lengths can be easily adjusted.
Central processing units (CPUs) are conventionally comprised of a basic control unit, an arithmetic logic unit (ALU), and several general/special purpose registers. All of which elements are now routinely integrated on a single monolithic semiconductor substrate as a direct result of advancements in semiconductor processing technology. The control unit, ALU, and registers are usually interconnected by various proprietary kinds of intra-chip buses (sometimes called micro-buses). Program commands and I/O data flow over these buses. The internal connections between the elements dramatically reduce the number of external connections that would otherwise be necessary. Quality and reliability experts have a rule-of-thumb that says a reduction in the number of external pins and their PC board connections will be directly reflected in an improvement in a system's reliability. Individual device reliability is often computed on the basis of how many pins the IC's in a system have. But high levels of integration reduce the flexibility a system designer has with customizing the architecture for particular applications. Since the interconnects are on-chip, they are not accessible to board and systems designers. So these engineers are stuck with whatever the chip designer decided to offer as a general compromise between conflicting applications that were envisioned at the time the chip was specified.
Each section and interconnect of a monolithic semiconductor CPU, quite naturally, has a fixed composition. Each CPU must therefore have a standardized fixed command (instruction) set. But non-monolithic implementations, even though they allow relatively mixing and matching each of the elements of a central processing unit, have serious disadvantages. For example, the required complex interconnections invite high failure rates. Being able to select a system optimal to its application is very compelling and can tip the scales in that direction.
A major advantage of semiconductor integrated circuit technology is that many electronic elements are microminiaturized at the same time in a single array. However, central processing units rarely have flat, non-hierarchical structures. For example, a command register receives program commands from program memory and then sends these commands to a command decoder. The command decoder deciphers the program commands and sends out micro-commands (also called microcode). More complex and larger instructions can make use of wider microcodes, and do more in parallel. Fewer instructions are needed to implement each step in a program. A reduction in power consumption is possible if the number of elements in a command that must be fetched can be reduced. Conversely, if the length of a command word is made shorter, the processing of the command can be reduced, because the decoding is less complicated, and timing generators can be simplified. High-speed processing is possible because faster clocks can be used.
Therefore, the present invention allows a chip having a command register, a command decoder, and a timing generator to be swapped in to and out from the rest of a CPU. This makes it easy to change command and instruction sets.